Computer Architecture Online Test

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The core element of parallel processing is __________.

1. Data sequencing.

2. Printer

3. CPU’s

4. Instruction execution

In _______________ operation a vector moves from memory to vector register.

1. Load vector operation

2. Store vector operation

3. Logical operation

4. Integer operation

_____________ is an operation that fetches the non-zero elements of a sparse vector from memory.

1. Strip mining

2. Gather

3. ETA-10

4. Scatter

Registers that are maintained by some of the processors for recording the condition of arithmetic as well as logical operations are called as _____________.

1. Branch registers

2. Non-condition code registers

3. Condition code registers

4. Re-locatable code

Define Mapping Process?

1. It is a process of detecting a word in cache.

2. It is a process that signifies the validity of locality of reference.

3. It is a process, which translates main memory address to cache memory address.

4. It is a process of transforming data from main memory to cache memory.

Consider the following statements with respect to MPP: If a fault occurs during computation, the sequence of instructions following the last dump to local memory must be repeated after replacement of the fault-containing column. The processing elements are linked by a 2-dimension near-neighbor mesh and this g ives an advantage of high bandwidth. State True or False:

1. 1-False, 2-False

2. 1-True, 2-False

3. 1-True, 2-True

4. 1-False, 2-True

In pipelining, two or more instructions that are independent of each other can overlap. This possibility of overlap is known as ____________. Case of DLX (DLX is a RISC processor architecture) pipeline, the structural & data hazards are examined during the ____________.

1.Instruction level parallelism, Instruction decode

2. Floating point registers, Structural hazards

3. Structural hazards, Data hazard

4. Instruction decode, Instruction level parallelism

Consider the following statements with respect to parallelism in pipelining: When two or more instructions that are independent of each other, overlap, they are called Dynamic Scheduling. Straight line parallelism is always greater than loop level parallelism. State True or False:

1. 1-False, 2-True

2. 1-True, 2-False

3. 1-True, 2-True

4. 1-False, 2-False

What was used to store small amount of bytes of data?

1. RAM

2. Disks

3. Tape drives

4. Punch cards

A common foundation or paradigm th at links the computer architect. The __________ operates by manipulati ng symbols on a tape.

1. Turing machine architecture, Computational Model

2. Turing machine architecture, Von-Neumann architecture

3. Computational model, Turing machine architecture

4. Von-Neumann architecture, Dataflow architecture

Consider the following statements with respect to RAIDS: BIP is an acronym for Block-interleaved parity and is equivalent to RAID Magnetic d isks help provide information when the disk fails as the information is recorded in each sector that helps detect errors. State True or False:

1. 1-False, 2-False

2. 1-True, 2-False

3. 1-False, 2-True

4. 1-True, 2-True

__________ mapping is used in cach e organisation which is the quickest and most supple organisation.

1. Sequential

2. Associative

3. Direct

4. Set associative

Which function can fetch and issue instruction s from a queue or latch?

1. ID

2. EX

3. DLX

4. IF

Consider the below mentioned statements with respect to dataflow graph: Dataflow graph is also called as flow dependency graph. Dataflow graph is as ynchronous as execution of a node starts when matching data is available at a node's input ports. State True or False:

1. 1-False, 2-True

2. 1-True, 2-True

3. 1-False, 2-False

4. 1-True, 2-False

The fourth generation of computers (1978-till date) was marked by use of _________.

1. Integrated Circuits

2. Vacuum Tubes

3. Large-Scale Integrated (LSI) circuits

4. Transistors

A normal CPU operates on __________.

1. Vector

2. Multiple vectors

3. Multiple scalars

4. One scalar at a time.

__________ executes only the instructions that are commonly used in programs and thus, makes the processor simpler. __________ consists of variety expert instructions and may just not be freq uently used in practical programs.

1. Reduced instruction set computer (RISC), Complex instruction set computer (CISC)

2. Complex instruction set computer (CISC), Very long instruction word (VLIW)

3. Very long instruction word (VLIW), Reduced instruction set computer (RISC)

4. Reduced instruction set computer (RISC), Very long instr uction word (VLIW)

In the late 1970s, we observed the emerging of ___________ that were high-performance computers for scientific computing. In 1960s, the ____________ used to be the most prevalent ones.

1. Processors, Microprocessors

2. Microcomputers, Supercomputers

3. Supercomputers, Main-frame computers

4. Main-frame computers, Microcomputers

___________ the pipeline solution is considered attractive due to its simplicity for hardwa re and software.

1. Flush

2. Instruction count-0xFF01

3. Load-stall count-0xFF02

4. Program counter

The Cray-1usually had a performance of about ______________, but with up to three chains running, it could hit the highest point at ___________.

1. 80 MFLOPS, 120 MFLOPS

2. 120 MFLOPS, 240 MFLOPS

3. 80 MFLOPS, 240 MFLOPS

4. 80 MFLOPS, 140 MFLOPS

Consider the following statements with respect to the number of pipeline stages used to perform a given task: Specification of the subtasks to be performed in only first stage of the pipeline. Layout of the stage sequence, i.e., whether the stages are used in a strict sequential manner or some stages are recycled. State True or False:

1. 1-False, 2-False

2. 1-False, 2-True

3. 1-True, 2-False

4. 1-True, 2-True

___________ units are generally floating-point units that are completely pipelined.

1. Vector load and store unit

2. Vector functional unit

3. Control unit

4. Scalar registers

___________ execution is the temporal behavior of the N-client 1-server model where one clie nt is served at any given moment.

1. Multiple data

2. Single data

3. Parallel

4. Concurrent

How many distinct functional units are present in CDC6600?

1. 5

2. 4

3. 16

4. 7

_____________ is a register that temporarily stores the data that is to be written in the memory or the data received from the memory. ______________ identifies the address of memory location from where the data or instruction is to be accessed or where the data is to be stored.

1. Instruction Register, Memory Address Register

2. Memory Buffer Register, Memory Address Register

3. Me mory Address Register, Instruction Register

4. Memory Address Register, Memory Buffer Register

In pipelining, the CPU executes each instruction in a series of following stages:

Instruction Fetching (IF)-----> Instruction Decoding (ID)-----> Instruction Execution (EX)-----> and Register Write back (WB).

1. Non-linear pipelines

2. Structural hazards

3. Linear pipelines

4. Memory access (MEM)

The equation of average memory access time = Hit time + ___________ x _______________.

1. Miss penalty, Cache size

2. Miss rate, Miss penalty

3. Cache size, Miss penalty

4. Miss penalty, Hit time

What does drive D or E symbolise?

1. Floppy drive

2. Second floppy drive

3. Hard disk

4. CD-ROM drive

Consider the following statements with respect to data hazards: In pipelining, the control hazards arise when the sequence of read/write accesses to operands. Pipelining has a major effect on changing the relative timing of instructions by executing them at the same time. This leads to data and control hazards. State True or False:

1. 1-True, 2-False

2. 1-False, 2-False

3. 1-True, 2-True

4. 1-False, 2-True

In which command, the interface responds by transmitting data?

1. Control

2. Status

3. Data output

4. Data input

The scalar registers are also linked to the functional uni ts with the help of t he pair of _____________.

1. Horizontal bars

2. Crossbars

3. Straight bars

4. Vertical bars

The smallest unit of memory that the CPU can read or write is ____________.

1. Field

2. Word

3. Cell

4. Mode

__________ is the logical structure of a computer’s Random-Access Memory (RAM).

1. Address field

2. Addressing mode

3. Operation field

4. Memory addressing

_____________ is collecting the group of data elements distributed in memory and after that placing them in linear sequential register files.

1. Vectorisa tion

2. Pipelining

3. Vector register

4. Memory

___________ address of the operand calculated during the prior cycle is used to access memory.

1. Instruction decode fetch cycle

2. Instruction fetch cycle

3. Memory access fetch cycle

4. Memory access completion cycle

Consider the design aspects of a CM5 system with 32 processor and state which of the below options is true?

1. Peak speed of 128

2. 0 synchronisation time

3. 128 data paths

4. Memory of 32 Gbyte

__________ occur from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution. __________ occurs when an instruction depends on the result of a previous instructi on in a way that is exposed by the overlapping of instructions in the pipeline.

1. Cache miss, Hazard in pipeline

2. Structural hazards, Data hazards

3. Control hazards, Cache miss

4. Control hazards, Structural hazards

Consider the following statements with respect to instructions for control flow: In a program con trol type of instruction, execution of instruction may change the address value in the program counter and cause the flow of control to be altered. Once a data transfer or data manipulation instruction is executed, control returns to the decode cycle wi th the program counter containing the address of the instruction next in sequence. State True or False:

1. 1-False, 2-False

2. 1-True, 2-True

3. 1-True, 2-False

4. 1-False, 2-True

__________ is systems with multiple CPUs, which are capable of independently executing different tasks in parallel. In this category every processor and memory module has similar access time.

1. UMA, Microprocessor

2. Microprocessor, Multiprocessor

3. Multiprocessor, UMA

4. UMA, NUMA

In which of the following cases, any completing instruction may not be permitted to write its result?

1. If the scoreboard has not detected any WAR hazard

2. Existence of any instruction which has read its operand

3. One of the operands is the same as the result of the completing instruction

4. Operands which d o not have the same register as destination

The high-level attributes of a computer’s architecture, such as the memory system, the memory integration and the architecture of the internal processor or CPU, are components of the term ___________.

1. Organisation

2. Instruction set

3. Hardware

4. Software

Consider the below mentioned statements with respect to virtual address mode. In the virtual address mode, cache access efficiency is faster than physical addressing mode. In the virtual address mode, cache lookup is delayed. State True or False:

1. 1-True, 2-True

2. 1-False, 2-True

3. 1-True, 2-False

4. 1-False, 2-False

Layout and _________ are the two aspects of branch processing.

1. Micro-architectural implementation

2. Branch detection

3. Accessing the branch target path

4. Handling of unresolved conditional branches

Fine-grain threading is considered as a ______ threading.

1. Function-level

2. Loop level

3. Task-level

4. Instruction-level

___________ states that “the performance improvement to be gained from using some faster mode of execution is limited by the fraction of the time the faster mode can be used.”

1. Hybrid technique

2. Principle of locality

3. Variable length technique

4. Amdahl’s Law

The ____________ should be checked for correctness. ______________ means either stores can bypass loads or vice versa, without violating the memory data dependencies.

1. Reorder buffer, Load and store reordering

2. Memory consistency, LMD

3. Speculative loads, Load/Store bypassing

4. Processor consistency, Reorder buffer

____________ design separates the testing for condition as well as branching. It is followed by Pentium which makes use of a flag register for recording the outcome of the test conditions.

1. Set-then-jump

2.Condition code register

3.Test-and-jump

4. PC-relative

In dynamic scheduling, the hardware ______________ the instruction execution to reduce stalling of pipeline.

1. Rearranges

2. Bypasses

3. Forwards

4. Unhide

_________ consists of a variety expert instruction and may just not be frequently used in practical programs.

1. Reduced instruction set computer

2. Very short instruction word

3. Complex instruction set computer

4. Very long instru ction word

It deals with the issue of selection of hardware components and interconnecting them to create computers that achieve specified functional, performance and cost goals.

1. Computational Model

2. Von-Neumann Architecture

3. Computer Architecture

4. Execution Model

__________ is used to reduce cache hit time.

1. Avoiding address tra nslation during cache indexing

2. Early restart and critical word first

3. Giving priority to read misses over writes

4. Pseudo-associative caches

_______ is a memory-memory vector machine and fetches vectors directly from memory to load the pipelines as well as stores the pipeline outcomes directly to memo ry.

1. CFC Cyber 205

2. CDC Cyber 205

3. CCD Cyber 205

4. CCF Cyber 205

For using _________ technique, compiler should have the entire knowledge of system and its timings.

1. Multithreading

2. Application of cache memory

3. Non-blocking writes

4. Pre-fetching

In _____________ each address field determines two address fields i.e. either a memory word or the processor register.

1. Zero-address instructions

2. Two-address inst ructions

3. One-address instructions

4. Three-address instructions

The ALU performs the indicated operation on the operands prepared in the prior cycle and store the result in the specified destination operand location.

1. Decode instruction

2. Fetch operand

3. Execute instruction

4. Fetch instruction

In this mode, the instruction specifies a register in the CPU that contains the address of the operand and not the operand itself.

1. Immediate Mode

2. Register Mode

3. Register Indirect Mode

4. Auto-increment or Auto-decrement Mode

CPA stands for _____________.

1. Complex-process application

2. Carry-processor adder

3. Carry-propagation adder

4. Computer-propagation adder

_________ in a dataflow graph represent data paths.

1. Data links

2. Sticky tokens

3. Nodes

4. Edges

______________ must be able to deal with both register and memory operands as well as destinations.

1. RISC pipelines

2. Load/Store by-passing

3. CISC pipelines

4. Branch instructions

The configuration, in which no difference between memory and I/O devices is seen by the CPU, is referred to as ________.

1. Memory-mapped I/O

2. Memory address register

3. Memory unit

4. Memory unit

The beginning of the archite cture of Itanium processor took place at ________.

1. Microsoft

2. Hewlett-Packard

3. Dell

4. Intel

___________ is used to reduce cache hit time.

1. Avoiding address translation during cache indexing

2. Pseudo-associative caches

3. Giving priority to read misses over writes

4. Early restart and critical word first

__________ occur when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipel ine.

1. Data hazards

2. Structural hazards

3. Control hazards

4. Hazard in pipeline

_________ is a method which is basically utilised for handling the problems related to branch. ___________ helps in instru ction execution. It receives branch instructions and resolves the conditional branches as early as possible.

1. Intel IA-64 architecture, RISC

2. Branch prediction, Branch processing

3. PC register, Branch pre diction

4. Branch processing, Intel IA-64 architecture

Which is the simplest scheme to handle branches?

1. Assume each branch as taken

2. Predict-not-taken or predict-untaken scheme

3. Assume each branch as not-taken

4. Freeze or Flush the pipeline

Consider the following statements with respect to I/O performance measures: Throughput is the average number of tasks completed by the server over a period of time. The two most common measures of I/O performance, used currently, are throughput and response time. State True or False:

1. 1-True, 2-True

2. 1-False, 2-False

3. 1-False, 2-True

4. 1-True, 2-False

Which of the following storage devices require constant electri city?

1. Disks

2. Hard drive

3. RAM

4. Tape drive

The term RISC stands for _______________.

1. Reduced Instruction Set Computing

2. Random Instruction Set Computing

3. Register Instruction Set Computing

4. Reduced Instruction Set Compiler

Ease-of-use and extensive graphic capabilities are the important character istics of ___________.

1. Desktop computers

2. Minicomputers

3. Micro-computers

4. Servers

In the year 1834, Babbage attempted to build a digital computer, called ___________.

1. IAS machine

2. Analytical engine

3. Difference engine

4. Pascaline

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